In the following we give a pseudo-formal semantics for UPPAAL. The semantics defines a timed transition system (S, s0, →) describing the behaviour of a network of extended timed automata. The set of states S is defined as {(L, v) | v ⊨ Inv(L)}, where L is a location vector, v is a function (called a valuation) mapping integer variables and clocks to their values, and Inv is a function mapping locations and location vectors to invariants. The initial state s0 is the state where all processes are in the initial location, all variables have their initial value, and all clocks are zero. The transition relation, →, contains two kinds of transitions: delay transitions and action transitions. We will describe each type below.
Given a valuation v and an expression e, we say that v satisfies e if e evaluates to non-zero for the given valuation v.
If during a successor computation any expression evaluation is invalid (consult the section on expressions for further details about invalid evaluations), the verification is aborted.
Delay transitions model the passing of time without changing the current location. We have a delay transition (L, v) −d→ (L, v’), where d is a non-negative real, if and only if:
For action transtions, the synchronisation label of edges is important. Since UPPAAL supports arrays of channels, we have that the label contains an expression evaluating to a channel. The concrete channel depends on the current valuation. To avoid cluttering the semantics we make the simplifying assumption that each synchronisation label refers to a channel directly.
Priorities increase the determinism of a system by letting a high priority action transition block a lower priority action transition. Note that delay transitions can never be blocked, and no action transition can be blocked by a delay transition.
For action transitions, there are three cases: Internal transitions, binary synchronisations and broadcast synchronisations. Each will be described in the following.
We have a transition (L, v) −*→ (L’, v’) if there is an edge e=(ℓ,ℓ’) such that:
We have a transition (L, v) −*→ (L’, v’) if there are two edges e1=(ℓ1,ℓ1’) and e2=(ℓ2,ℓ2’) in two different processes such that:
Assume an order p1, p2, … pn of processes given by the order of the processes in the system declaration statement. We have a transition (L, v) −*→ (L’, v’) if there is an edge e=(ℓ,ℓ’) and m edges ei=(ℓi,ℓi’) for 1≤i≤m such that:
In statistical model checking the concrete delay and transition are determined as follows:
Since Statistical model checking uses numerical simulations and statistics rather than symbolic operations, it allows many features like arbitrary derivatives over clock
variables, arbitrary guard and invariant expressions, including floating point expressions (which are not supported in Symbolic queries).
Current UPPAAL SMC implementation relies on numerical methods and has the following assumptions and limitations about the model:
broadcast
or there is always one process with an enabled receiving edge-transition.clock
variable) are assigned a uniform delay distribution, and states without an upper delay limit (invariant not constraining any clock
variable) are assigned an exponential distribution, therefore such locations may require an exponential rate to be defined.x==3.14
, or a combination of guard x>=3.14
and invariant x<=3.14
over clock
variable x
) require inifinite precision and thus cannot always be realized with adaptive integrator such as Runge-Kutta, thus such constraints need to be relaxed (e.g. replace guard with 3.14-eps<=x && x<=3.14
, or x>=3.14-eps
, where eps
is a precision constant). The precision of numerical integration can be controlled in Statistical Parameters.urgent broadcast chan
variable (no processes is required to listen to it).For example, see bouncing ball walk-through.
For more details about probabilistic semantics of priced timed automata please see:
Statistical Model Checking for Networks of Priced Timed Automata, Alexandre David, Kim G. Larsen, Axel Legay, Marius Mikučionis, Danny Bøgsted Poulsen, Jonas van Vliet and Zheng Wang. In Proceedings of the 9th International Conference on Formal Modeling and Analysis of Timed Systems (FORMATS), Aalborg, Denmark, September 2011.